High-performance crossbar interconnect for a VLIW video signal processor

A programmable Very Long Instruction Word (VLIW) Video Signal Processor (VSP) Chip is currently under development. The design of this chip provides some unique VLSI tradeoffs. The architecture requires flexible, high-bandwidth interconnect at fast cycle times. The design targets 32-64 operations per cycle at clock rates in excess of 500 MHz. A high-performance crossbar interconnect has been designed in a .25 μm process. Novel optimizations and design choices are presented that are unique to single-chip-processor crossbars. Area and speed tradeoffs are then examined for a variety of design parameters in order to guide architectural decisions for the VLIW VSP