High performance GaAs pseudo dynamic class of logic

Author

López, J.F. ; Sarmiento, R. ; Nùnez, A. ; Eshraghian, K.

Author_Institution

Centro de Microelectronica Aplicada, Univ. de Las Palmas, Gran Canaria, Spain

fYear

1996

fDate

23-27 Sep 1996

Firstpage

51

Lastpage

55

Abstract

In this paper Pseudo Dynamic Latched Logic (PDLL) is introduced. This class of logic takes benefits of both static and dynamic structures, by using a permanently refreshing circuitry which allows functionality even at low frequencies and high temperatures. Moreover, because of its dynamic structure, complex gates are possible with a subsequent delay-area-power reduction. PDLL performance is demonstrated by implementing a 4-bit carry lookahead adder fully operative in a range of 6 to 100°C. The adder operates at 0.8 GHz with an associated power dissipation of only 5.2 mW

Keywords

III-V semiconductors; adders; field effect logic circuits; gallium arsenide; 0 to 100 C; 0.8 GHz; 4 bit; 5.2 mW; GaAs; carry lookahead adder; high temperature; power dissipation; pseudo dynamic latched logic; refreshing circuitry; Adders; CMOS technology; Electrodes; Frequency; Gallium arsenide; High performance computing; Leakage current; Logic circuits; Logic devices; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.551962

Filename

551962