• DocumentCode
    3162984
  • Title

    Delay Analysis of the Distributed RC Line

  • Author

    Rao, Vasant B.

  • Author_Institution
    IBM EDA Laboratory, Hopewell Junction, NY
  • fYear
    1995
  • fDate
    1995
  • Firstpage
    370
  • Lastpage
    375
  • Abstract
    This paper reviews the step-response of the semi-infinite distributed RC line and focuses mainly on the step-response of a finite-length RC line with a capacitive load termination, which is the most common model for a wire inside the present day integrated CMOS chips. In particular, we obtain the values of some of the common threshold-crossing times at the output of such a line and show that even the simplest first order lumped II-approximation to the finite-length RC line terminated with a capacitive load is good enough for obtaining the 50% and 63.2% threshold-crossing times of the step-response. Higher order lumped approximations are necessary for more accurate predictions of the 10% and 90% threshold-crossing times.
  • Keywords
    Boundary conditions; Delay; Electronic design automation and methodology; Equations; Laboratories; Permission; Predictive models; Semiconductor device modeling; Voltage; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1995. DAC '95. 32nd Conference on
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-725-1
  • Type

    conf

  • DOI
    10.1109/DAC.1995.249975
  • Filename
    1586731