Distributed SPICE circuit model for ceramic capacitors

Discrete ceramic capacitors are used to achieve a low power supply impedance in the MHz range. The traditional series RLC circuit model for discrete capacitors is inadequate for low ESR capacitors when mounted on low ESL pads. When combined with other capacitors or power plane models, the simple RLC model does not correctly predict the magnitude or frequency of the anti-resonant peak formed by the parallel components. Discrete capacitors have higher ESR and lower inductance than expected at frequencies above series resonance. A new distributed circuit model is proposed for high Q, low ESR capacitors. The distributed model correlates well with hardware measurements. Both simulated and measured results indicate that anti-resonant peaks are higher in frequency and lower in magnitude than predicted by the traditional series RLC model. Low ESR capacitors do not create the high impedance peak expected from simulation of the traditional series RLC circuit model