DocumentCode :
3163065
Title :
Circuit partitioning using parallel mean field annealing algorithms
Author :
Bultan, Tevfik ; Aykanat, Cevdet
Author_Institution :
Dept. of Comput. Eng. & Inf. Sci., Bilkent Univ., Ankara, Turkey
fYear :
1991
fDate :
2-5 Dec 1991
Firstpage :
534
Lastpage :
541
Abstract :
Mean field annealing (MFA) algorithm, recently proposed for solving combinatorial optimization problems, combines the characteristics of neural networks and simulated annealing. Previous works on MFA resulted with successful mapping of the algorithm to some classic optimization problems such as travelling salesman problem and graph partitioning problem. In this paper, MFA is formulated for circuit partitioning problem (CPP) by using both graph and network models. Initial results of the implementations show that MFA can be used as an efficient alternative heuristic for CPP. MFA algorithms proposed for solving CPP are parallelized and implemented on an iPSC/2 hypercube multicomputer. Experimental results show that the proposed heuristics can be efficiently parallelized on hypercube multicomputers, which is crucial for algorithms solving such computationally hard problems
Keywords :
VLSI; circuit layout CAD; neural nets; simulated annealing; VLSI circuits; circuit partitioning; combinatorial optimization; graph partitioning problem; iPSC/2 hypercube multicomputer; neural networks; parallel mean field annealing algorithms; simulated annealing; travelling salesman problem; Circuit simulation; Computational modeling; Computer networks; Computer simulation; Hopfield neural networks; Hypercubes; Information science; Neural networks; Partitioning algorithms; Simulated annealing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing, 1991. Proceedings of the Third IEEE Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-2310-1
Type :
conf
DOI :
10.1109/SPDP.1991.218253
Filename :
218253
Link To Document :
بازگشت