Performance optimization and system clock determination for synthesis of DSP cores targeting FPGAs

In this paper, we present details of an integer linear programming (ILP) formulation for synthesis of high performance digital signal processing architectures targeting FPGA implementation. The formulation allows general multi-level chaining of operations in conjunction with multicycle and deeply pipelined function units. This novel ILP formulation simultaneously performs scheduling and binding while minimizing the architecture structural complexity, total execution time (rather than total cycle count), and determining the system clock duration. We demonstrate using high level synthesis benchmarks, that our approach explores larger solution space and obtains more efficient architectures as well as higher performance than previously possible with other synthesis approaches