Selection of base substrate material for design against interfacial delamination for a multilayered system-on-package (SOP) structure

System-On-Package (SOP) can reduce package size, increase functionality and improve performance at lower costs by embedding passives in a multilayered high-density wiring (HDW) structure. Due to the stringent warpage requirement for processing such a package, new base substrate materials are being explored with high modulus. The substrate will also have a CTE that is close to that of the die. The matched CTE will facilitate no-underfill attach flip-chips on SOP substrates. One major concern with the high-modulus “matched” CTE substrate is the potential interfacial delamination between different dielectric and metallization layers built-up on top of the base substrate. This research examines the possibilities of interfacial delamination in such a multilayered packaging structure under thermal loading. The objective of this paper is to evaluate the possibility of interfacial delamination of the new SOP integrated substrates with a primary focus on metallization copper and dielectric layer interface. An analytical model and numerical model have been developed to calculate the energy release rate of multilayered structures under thermal load. Based on the analysis results, a base layer material has been selected from a group of candidate materials. With this material as the base layer, the substrate has the minimum chance for a delamination to grow. The interfacial fracture toughness of copper/ViaLux^TM 81 PDDF has been measured. The energy release rate obtained from the analysis was compared with the interfacial fracture toughness, and the results indicate that there is minimal delamination growth under the given thermal load conditions. Based on analysis results, design recommendations for improving thermomechanical reliability are proposed