DocumentCode
3163302
Title
Standard cell floorplanning within the FHDL automatic placement tool
Author
Morency, Craig D. ; Maurer, Peter M.
Author_Institution
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
fYear
1990
fDate
1-4 Apr 1990
Firstpage
435
Abstract
Techniques which are being developed for the floorplanning of layouts in the Florida Hardware Design Language (FHDL) layout tool are present. These techniques show a different approach to the floorplanning of those layouts which are to contain a mixture of standard cells and macrocells. General cell placement and floorplanning are discussed. Standard cell collection, block generation, and placement optimization are discussed
Keywords
application specific integrated circuits; circuit layout CAD; integrated circuit technology; specification languages; ASIC design; CAD; FHDL; Florida Hardware Design Language; automatic placement tool; block generation; cell collection; floorplanning; layout tool; placement optimization; standard cells; Algorithm design and analysis; Circuit simulation; Computational modeling; Design automation; History; Integrated circuit layout; Integrated circuit packaging; Integrated circuit synthesis; Simulated annealing; Standards organizations;
fLanguage
English
Publisher
ieee
Conference_Titel
Southeastcon '90. Proceedings., IEEE
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/SECON.1990.117850
Filename
117850
Link To Document