Timing and power models for CMOS repeaters driving resistive interconnect

Author

Adler, Victor ; Friedman, Eby G.

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

fYear

1996

fDate

23-27 Sep 1996

Firstpage

201

Lastpage

204

Abstract

A delay and power model of a CMOS inverting repeater driving a resistive-capacitive load is presented. The model is derived from Sakurai´s alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time and exhibit less than 27% discrepancy from SPICE for a wide variety of RC loads. Expressions are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a resistive-capacitive interconnect line which are accurate to within 15% of SPICE for most practical loads

Keywords

CMOS logic circuits; integrated circuit interconnections; integrated circuit modelling; logic gates; repeaters; timing; CMOS inverting repeater; RC load; alpha-power law; delay model; power model; resistive-capacitive interconnect line; short-circuit power dissipation; timing model; Capacitance; Delay estimation; Integrated circuit interconnections; Inverters; Power dissipation; Propagation delay; Repeaters; SPICE; Semiconductor device modeling; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.551994

Filename

551994