An analytical approach to fine tuning in CMOS wave-pipelining

Author

Talukdar, Dipankar ; Sridhar, Ramalingam

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

fYear

1996

fDate

23-27 Sep 1996

Firstpage

205

Lastpage

208

Abstract

Fine tuning is an integral part of a wave-pipelined design process to achieve maximum clock speed. In this paper we present analytical approaches to two main components of the fine tuning process for CMOS designs, the computation of effective load capacitance at gate outputs and the transistor sizing of the driving gates to achieve equal rise and fall delay. Comparisons with Spice simulation results are presented to show the accuracy of the proposed approach

Keywords

CMOS logic circuits; capacitance; delays; integrated circuit design; logic design; pipeline processing; CMOS wave-pipelining; driving gates; effective load capacitance; fall delay; fine tuning; maximum clock speed; rise delay; transistor sizing; wave-pipelined design process; Capacitance; Circuit optimization; Circuit simulation; Clocks; Computational modeling; Delay effects; Integrated circuit interconnections; Inverters; Pipeline processing; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.551995

Filename

551995

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3163461