Title :
New architecture for high throughput-rate real-time 2-D DCT and the VLSI design
Author :
Jen-Shiun Chiang
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Tamsui
Abstract :
The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and is of great necessity to meet the requirement of high speed. In this paper, a new architecture for the VLSI design of 2-D DCT has been developed. This architecture contains the following features: (1) using the programmable logic array (PLA) to replace multipliers, (2) overlapped row-column operations and pipeline structure to reduce the total computation time, and (3) highly modular and regular structure for the efficient VLSI implementation. The architecture is implemented to a 8×8 2-D DCT. The circuit is designed by UMC´s 0.8 μm spdm CMOS process and the cell library is provided by ITRI CCL. The simulation is shown that the speed of the data processing for this DCT is more than 50 MHz. It performs equivalently 800 million multiplication and accumulations per second
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; discrete cosine transforms; programmable logic arrays; 0.8 micron; 50 MHz; CMOS circuit; VLSI design; architecture; data processing; discrete cosine transform; modular structure; overlapped row-column operations; pipeline structure; programmable logic array; real-time 2D DCT; throughput rate; CMOS logic circuits; CMOS process; Computer architecture; Digital images; Discrete cosine transforms; Image coding; Pipelines; Programmable logic arrays; Very large scale integration; Video compression;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551997
