DocumentCode
3163513
Title
Design of an ASIC architecture for high speed fractal image compression
Author
Ancarani, F. ; Gloria, A. De ; Olivieri, M. ; Stazzone, C.
Author_Institution
Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
fYear
1996
fDate
23-27 Sep 1996
Firstpage
223
Lastpage
226
Abstract
We report the results of the design and performance evaluation of an ASIC dedicated to fractal image compression. The ASIC is to be hosted on a PC platform by means of an interface board connected to the PCI bus. The obtained speed-up is 300 times with respect to the direct execution of the compression algorithm on a 100 MHz Pentium platform. The ASIC has been synthesized from VHDL and totals 150000 transistors
Keywords
application specific integrated circuits; data compression; digital signal processing chips; fractals; image coding; ASIC architecture; PC platform; PCI bus; VHDL; algorithm; design; high speed fractal image compression; interface board; Application specific integrated circuits; Compression algorithms; Fractals; Image coding; Iterative decoding; PSNR; Partitioning algorithms; Pixel; Reflection; Transform coding;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location
Rochester, NY
ISSN
1063-0988
Print_ISBN
0-7803-3302-0
Type
conf
DOI
10.1109/ASIC.1996.551998
Filename
551998
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