Micropipeline DSP-ASIC for a DS-SS receiver

Author

Oelmann, Bengt ; Tenhunen, Hannu

fYear

1996

fDate

23-27 Sep 1996

Firstpage

227

Lastpage

230

Abstract

This paper presents a fully asynchronous DSP for a Direct-Sequence Spread Spectrum (DS-SS) radio receiver. Issues relevant to micropipeline VLSI implementation and performance are discussed. The circuit has been designed using a standard cell library in 0.8 μm CMOS and contains 100,000 transistors. The receiver handles up to 48 million samples per second and the power consumption is 600 mW

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; asynchronous circuits; digital radio; digital signal processing chips; pipeline processing; radio receivers; spread spectrum communication; telecommunication computing; 0.8 micron; 600 mW; CMOS IC; DS-SS receiver; direct-sequence spread spectrum; fully asynchronous DSP; micropipeline DSP ASIC; micropipeline VLSI implementation; radio receiver; standard cell library; Circuits; Clocks; Delay estimation; Design methodology; Digital signal processing; Energy consumption; Logic; Receivers; Spread spectrum communication; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.551999

Filename

551999

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3163539