Challenge for future semiconductor development

Author

Hirose, M.

Author_Institution

Adv. Semicond. Res. Center, Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan

fYear

2002

fDate

6-8 Nov. 2002

Firstpage

2

Lastpage

3

Abstract

Progress in LSI technology has led to the concept of system-on-chip (SOC) that is still evolving to meet various applications for information processing and networking. SOC is composed of different IP cores such as MPU, RAM, RF, Analog, ASIC, DSP, Flash memory and even sensors. To realize high-performance and low power consumption in SOC, the design and fabrication of such complex systems need to overcome difficult technology roadblocks. This paper reviews key issues on 65 to 45nm node CMOS technology and related R&D challenges, together with the future prospects of silicon technology.

Keywords

CMOS integrated circuits; elemental semiconductors; integrated circuit design; low-power electronics; silicon; system-on-chip; 65 to 45 nm; CMOS technology; LSI technology; SOC; Si; future semiconductor development; low power consumption; silicon technology; system-on-chip; technology roadblocks; Application specific integrated circuits; CMOS technology; Digital signal processing; Energy consumption; Flash memory; Information processing; Large scale integration; Radio frequency; Read-write memory; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocesses and Nanotechnology Conference, 2002. Digest of Papers. Microprocesses and Nanotechnology 2002. 2002 International

Conference_Location

Tokyo, Japan

Print_ISBN

4-89114-031-3

Type

conf

DOI

10.1109/IMNC.2002.1178514

Filename

1178514