• DocumentCode
    3163640
  • Title

    Efficient error bit identification from failing signatures

  • Author

    Stroud, Charles E. ; Damarla, T. Raju

  • Author_Institution
    Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
  • fYear
    1996
  • fDate
    23-27 Sep 1996
  • Firstpage
    259
  • Lastpage
    262
  • Abstract
    Efficient identification of bit errors in the input to single and multiple input signature registers is obtained using a characteristic polynomial constructed from the product of multiple polynomials. This set of multiple polynomials may be primitive and/or non-primitive but must have different orders. The degree of the input polynomial to the signature register is limited to the least common multiple of the orders of these polynomials. The identification algorithm is based on look-up tables with the total number of entries equal the sum of the orders of these polynomials, making the technique more efficient than previous approaches in terms of both hardware and algorithmic complexity
  • Keywords
    built-in self test; digital integrated circuits; identification; integrated circuit testing; integrated logic circuits; logic testing; polynomials; table lookup; BIST; characteristic polynomial; error bit identification; failing signatures; identification algorithm; lookup tables; multiple input signature registers; single input signature registers; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault diagnosis; Hardware; Polynomials; Registers; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
  • Conference_Location
    Rochester, NY
  • ISSN
    1063-0988
  • Print_ISBN
    0-7803-3302-0
  • Type

    conf

  • DOI
    10.1109/ASIC.1996.552006
  • Filename
    552006