Optimal circuit design for low power CMOS GSI

Author

Bhavnagarwala, Azeez J. ; De, Vivek K. ; Austin, Blanca ; Meindl, James D.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

1996

fDate

23-27 Sep 1996

Firstpage

313

Lastpage

316

Abstract

For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60°K above room temperature

Keywords

CMOS integrated circuits; ULSI; circuit optimisation; integrated circuit design; integrated circuit modelling; integrated circuit technology; 0.25 micron; MOSFET models; low power CMOS GSI; operating temperature ranges; optimal circuit design; static CMOS datapath; total power dissipation reduction; CMOS technology; Circuit synthesis; Circuits and systems; MOSFET circuits; Performance loss; Power dissipation; Power system modeling; Semiconductor device modeling; Temperature distribution; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.552022

Filename

552022