DocumentCode
3164048
Title
Interface constrained processor specification and scheduling
Author
Greenbaum, Jack ; Brewer, Forrest
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear
1992
fDate
28-29 Feb 1992
Firstpage
168
Lastpage
175
Abstract
The authors propose a novel specification for tightly constrained processing elements based on recognizing concurrent sequences of data flow. This specification has several benefits, notably it allows a very concise representation of complex internal semantics and interface protocols. Particular advantages exist with specifying timing constraints and performance cost functions for control dominated applications. The specification can be made canonical and leads to an interesting formulation of the scheduling problem
Keywords
formal specification; protocols; scheduling; specification languages; concurrent sequences; data flow; interface constrained processor specification; interface protocols; performance cost functions; scheduling; tightly constrained processing elements; timing constraints; Communication system control; Control systems; Cost function; Hardware design languages; Humans; Lifting equipment; Microprocessors; Processor scheduling; Protocols; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1992., Proceedings of the Second Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-2610-0
Type
conf
DOI
10.1109/GLSV.1992.218349
Filename
218349
Link To Document