Quadtree interconnection network layout

Quadtree data structure has been used in a number of applications. However, VLSI embedding of quadtree based parallel architecture using grid model has not been studied. This paper studies VLSI embedding of quadtree using grid model. H-tree layout for binary tree is extended for trivial quadtree layout, followed by two layout strategies for rectangular grids. Two generic layout styles (standard layout and X -layout) are proposed for higher order grids (e.g., hexagonal and octagonal grids). Base tile layout patterns are proposed for area compaction with recursive X-layout. In each case, layout dimensions and I/O bandwidth are computed. The authors demonstrate how the two generic layouts can be mixed to obtain higher I/O bandwidth and estimate the area sacrifice. An improved recursive layout mixing strategy is proposed