DocumentCode :
3164373
Title :
The parallel complexity of minimizing column conflicts
Author :
Savage, John E. ; Wloka, Markus G.
Author_Institution :
Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
fYear :
1992
fDate :
28-29 Feb 1992
Firstpage :
30
Lastpage :
34
Abstract :
Two-layer channel routers typically require a post-processing phase to reduce or eliminate column conflicts. Attempts have been made to parallelize this problem using local search heuristics that swap horizontal channel wire segments. The authors show that all such heuristics for this problem are P-hard and unlikely to be efficiently parallelizable
Keywords :
circuit layout CAD; computational complexity; P-hard; heuristics; minimizing column conflicts; parallel complexity; two-level channel routers; Computer science; Cost function; Joining processes; Minimization methods; Parallel machines; Phase change random access memory; Polynomials; Routing; Simulated annealing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1992., Proceedings of the Second Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2610-0
Type :
conf
DOI :
10.1109/GLSV.1992.218368
Filename :
218368
Link To Document :
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