A 30 MIPS VLSI CPU

Author

Boschma, B.D. ; Burns, D.M. ; Chin, R. ; Fiduccia, N.S. ; Hu, C. ; Reed, M.J. ; Rueth, T.I. ; Schumacher, F.X. ; Shen, V.

Author_Institution

Hewlett-Packard Co., Cupertino, CA, USA

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

82

Lastpage

83

Abstract

A description is given of a VLSI CPU which implements an existing 32-b architecture with a set of 140 instructions, most of which can be executed within one effective clock cycle. The device is fabricated in an nMOS process with three metal layers having minimum metal-1 line width of 1.5 mu m and drawn device lengths of 1.7 mu m. The die, containing 183000 transistors, is 1.4 cm*1.4 cm. The CPU directly addresses external SRAMs organized as a two-way set-associative split 512-kb-instruction/512-kb-data cache. Separate instruction and data paths allow for concurrent overlapped cache memory access. Chip specifications are presented, and the CPU data path is shown.<>

Keywords

VLSI; field effect integrated circuits; microprocessor chips; pipeline processing; 1.5 micron; 1.7 micron; 30 MIPS; 32 bit; 32-b architecture; VLSI CPU; concurrent overlapped cache memory access; external SRAM addressing; five stage instruction pipeline; nMOS process; three metal layers; Atherosclerosis; Central Processing Unit; Clocks; Delay; Electronics packaging; FETs; Metallization; Pipelines; Solid state circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48191

Filename

48191