Lithography process development for 20 nm MOSFET devices

The authors propose a new method to obtain 20 nm patterns during the lithographic process step with a self-generated hard mask This process mixes two resists: hydrogensilsquioxane (HSQ) and chemically amplified resist (CAR) Sumitomo NEB22A2. It relies on splitting the pattern into high resolution and low-resolution features. By this method, hard mask patterns with the gate lower than 20 nm have already been produced without using resist or hard mask trimming. This technique leads to a vertical profile with no oxide pitting even after 75 nm polysilicon etching.