A 5 V-only 256 kbit CMOS flash EEPROM

Author

D´Arrigo, S. ; Imondi, G. ; Santin, G. ; Gill, M. ; Cleavelin, R. ; Spagliccia, S. ; Tomassetti, E. ; Lin, S. ; Nguyen, A. ; Shah, P. ; Savarese, G. ; McElroy, D.

Author_Institution

Texas Instrum. Inc., TX, USA

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

132

Lastpage

133

Abstract

The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and a merged-pass-gate transistor. The process is array-contactless EEPROM (ACEE), with buried source/drain for the bit lines with a tunnel oxide module and a 20-V CMOS module. The program and erase operations employ the Fowler-Nordheim current tunneled through 100-AA oxide when the proper electrical voltages are applied to the selected bit. The device and technology parameters are summarized.<>

Keywords

CMOS integrated circuits; EPROM; 256 kbit; 5 V; CMOS; Fowler-Nordheim current; array-contactless; buried source/drain; electrically erasable; flash EEPROM; floating-gate transistor; merged-pass-gate transistor; programmable read-only memory; single power supply; tunnel oxide module; Charge pumps; Circuits; Costs; EPROM; Pulse generation; Stress; Time measurement; Timing; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48207

Filename

48207