A 12 b 500 ns subranging ADC

The author describes a 12-b, 500-ns subranging A/D (analog/digital) converter which includes a voltage reference, a clock generator, and full microprocessor-bus-interface control logic. The subranging architecture includes analog and digital correction, which reduces the accuracy requirements of the reference levels and the comparator offsets in the quantizers. The circuit is fabricated on an 8-GHz-/sub fT/, 2- mu m oxide-isolated bipolar process and uses TiW fuses to trim the nonlinearity of the DACs (digital/analog converters), the voltage reference, and the full scale and zero scale of the A/D. In the present implementation of subranging with correction, the subtraction DACs need not settle to 12-b precision before the comparators in the next quantizer are strobed, except in the final step. The digital encoding and correction logic path is separate from the analog signal path. The logic power consumption is kept low since the delay through this path does not affect conversion speed. The circuit topology and the process capabilities have resulted in a 500-ns 12-b A/D converter dissipating 600 mW in 39k mil/sup 2/. A block diagram of the A/D implementation is shown.<>