DocumentCode
3165046
Title
Design considerations for 32-bit microprocessor TX3
Author
Okamoto, Kosei ; Miyata, Misao ; Kishigami, Hidechika ; Miyamori, Takashi ; Sato, Tai
Author_Institution
Toshiba Corp., Ibaraki, Japan
fYear
1988
fDate
Feb. 29 1988-March 3 1988
Firstpage
25
Lastpage
29
Abstract
The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction loop buffer, three instruction execution units, and the ability to issue up to two instructions per cycle.<>
Keywords
instruction sets; microprocessor chips; 32 bit; 32-bit microprocessor TX3; 8-kB data cache; 8-kB instruction cache; TRON-CHIP32 specification; decoded instruction loop buffer; design considerations; instruction set; Decoding; Laboratories; Memory management; Microprocessors; Operating systems; Pipelines; Registers; Semiconductor devices; User interfaces; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-0828-5
Type
conf
DOI
10.1109/CMPCON.1988.4822
Filename
4822
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