• DocumentCode
    3165192
  • Title

    Evaluation and optimization of package processing, design, and reliability through solder joint profile prediction

  • Author

    Yeung, Betty H. ; Lee, Tien-Yu Tom

  • Author_Institution
    Interconnect Syst. Labs., Motorola Inc., Tempe, AZ, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    925
  • Lastpage
    930
  • Abstract
    Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design
  • Keywords
    flip-chip devices; packaging; reliability; soldering; Surface Evolver software; analytical model; bump shape; design optimization; flip-chip assembly; joint shape; reliability; solder processing; wafer-level bumping; wafer-level packaging; Analytical models; Application software; Assembly; Chip scale packaging; Design optimization; Process design; Shape; Software packages; Soldering; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2001. Proceedings., 51st
  • Conference_Location
    Orlando, FL
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-7038-4
  • Type

    conf

  • DOI
    10.1109/ECTC.2001.927906
  • Filename
    927906