A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor

Author

Benschneider, B.J. ; Bowhill, W.J. ; Cooper, E.M. ; Gavrielov, M.N. ; Gronowski, P.E. ; Maheshwari, V.K. ; Peng, V. ; Pickholtz, J.D. ; Samudrala, S.

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

50

Lastpage

51

Abstract

A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors.<>

Keywords

CMOS integrated circuits; digital arithmetic; microprocessor chips; pipeline processing; 1.5 micron; 50 MHz; 64 bit; CMOS technology; divider; double-precision floating-point operations; five-segment execution core; floating-point arithmetic processor; fully pipelined stages; integer multiplication; interface section; single-precision floating point; superminicomputer architecture standard; CMOS process; CMOS technology; Decoding; Detectors; Ducts; Floating-point arithmetic; Pipelines; Programmable logic arrays; Sensor arrays; Signal detection;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48229

Filename

48229