High performance flip chip PBGA development

Flip Chip PBGA has been identified as a high performance packaging solution to meet the growing need for products with increased electrical performance, greater I/O density, and high system reliability. The development of a FC-PBGA presents several challenges due primarily to its sensitivity to moisture and the CTE mismatch between the silicon die and organic substrate. Potential risks and failure modes are encountered at all phases of environmental stressing. Moisture sensitivity is an obstacle in maintaining interfacial adhesion between the die surface and the underfill that is required to buffer the CTE mismatch. This critical interface becomes stressed during Moisture Pre-Conditioning, potentially leading to delamination. Once the adhesion issue is resolved, the underfill material will solidly couple the die to the substrate. The coupling is critical to minimizing bump interconnect fatigue, however, it also results in bending that may cause die cracking during thermal cycling. Additionally, fatigue in the organic substrate may develop during extended thermal cycling leading to further failure modes. The focus of this paper will be the development of the package materials and mechanical design, which were addressed subsequent to the successful development of a robust assembly process. The paper will discuss the challenges identified and overcome during package development that resulted in the successful qualification and introduction of a high performance Flip Chip PBGA package. It will discuss modeling and empirical identification of the primary failure modes and present approaches for addressing them. Through material selection, package design, and compatibility of the assembly process these obstacles can be overcome, resulting in a package suitable for markets requiring high electrical performance, high pin counts, and high system reliability