DocumentCode
3165737
Title
A CMOS sub-harmonic mixer for direct conversion receiver
Author
Lee, Jeongeo ; Liuyang ; Choi, Sungjoo ; Lee, Jaeseok ; Kim, Hyeongdong
Author_Institution
Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea
fYear
2009
fDate
7-10 Dec. 2009
Firstpage
1695
Lastpage
1698
Abstract
A sub-harmonic passive mixer for WiBro (2.3~2.4GHz) in 0.18 ¿m CMOS process has been designed. The circuit includes a differential phase splitter for the LO circuit. This architecture have a low flicker noise (20.29Hz) and a good double sideband noise figure (9.29dB) while demanding little power consumption. The input referred 1-dB compression point is -4.3dBm, IIP2 is 33.12dBm and IIP3 is -3.44dBm. In this paper, it is to understand the mechanism of SHM.
Keywords
CMOS analogue integrated circuits; UHF mixers; passive networks; radio receivers; CMOS sub-harmonic passive mixer; differential phase splitter; direct conversion receiver; local oscillator circuit; size 0.18 mum; 1f noise; CMOS process; Circuits; Filters; Image converters; Mixers; Noise figure; Radio frequency; Resistors; Switches; CMOS; WiBro; direct Conversion receiver; poly-phase filters(PPF); sub-harmonic mixer (SHM);
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference, 2009. APMC 2009. Asia Pacific
Conference_Location
Singapore
Print_ISBN
978-1-4244-2801-4
Electronic_ISBN
978-1-4244-2802-1
Type
conf
DOI
10.1109/APMC.2009.5384300
Filename
5384300
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