Integrated modeling methodology for core and I/O power delivery

Traditionally core power delivery and I/O signal analysis were performed separately to analyze the performance of a microprocessor package. The coupling between I/O and core power delivery was assumed negligibly small. In this paper, we describe a methodology to for analyzing core and I/O power delivery using the same integrated model. Having an integrated model allows us to study the noise induced on the core power nets due to switching currents on the I/O nets and vice-versa. Having an integrated model also gives us the opportunity to study the relative merits of separating or combining the core and I/O power networks