The M/sup 2/ hierarchical multiprocessor

Author

Oyang, Yen-Jen ; Sheu, David Jinsung ; Cheng, Chih-Yuan ; Yang, Cheng-Zen

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1992

fDate

4-8 May 1992

Firstpage

41

Lastpage

46

Abstract

The design and development of a bus-based hierarchical multiprocessor named M/sup 2/ is discussed. The primary design goal of the M/sup 2/ was to derive a multiprocessor architecture that features a much higher degree of scalability than the shared-memory shared-bus architecture and exploits parallelism at both medium- and coarse-grain levels. Compared with other hierarchical multiprocessors, the M/sup 2/ is distinctive in its memory configuration, which is aimed at avoiding severe inter-CPU interference due to page-swapping events. Compared with a group of multiprocessors connected by a local area network, the M/sup 2/ enjoys higher scalability due to higher bandwidth of the backplane bus.<>

Keywords

computer interfaces; multiprocessing systems; shared memory systems; M/sup 2/; backplane bus; bandwidth; bus-based hierarchical multiprocessor; coarse-grain levels; hierarchical multiprocessors; inter-CPU interference; local area network; memory configuration; multiprocessor architecture; page-swapping events; primary design goal; scalability; shared-memory shared-bus architecture; Backplanes; Communication system control; Hardware; Interference; Memory architecture; Operating systems; Parallel processing; Prototypes; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '92 . 'Computer Systems and Software Engineering',Proceedings.

Conference_Location

The Hague, Netherlands

Print_ISBN

0-8186-2760-3

Type

conf

DOI

10.1109/CMPEUR.1992.218489

Filename

218489