A large-grain data flow architecture utilizing multiple levels of parallelism

Author

Zehendner, Eberhard ; Ungerer, Theo

Author_Institution

Dept. of Math., Augsburg Univ., Germany

fYear

1992

fDate

4-8 May 1992

Firstpage

23

Lastpage

28

Abstract

A data flow architecture is presented that utilizes several levels of parallelism by a three-level hierarchical hardware structure. Task level parallelism was exploited by the architectural structure of a distributed memory multiprocessor and a load distribution strategy that supports parallel execution of procedure activations. Block and instruction level parallelism was utilized by token-passing, similar to large-grain data flow. Subinstruction level parallelism was exploited by single instruction, multiple data (SIMD) evaluation of complex machine instructions.<>

Keywords

distributed memory systems; parallel architectures; resource allocation; architectural structure; complex machine instructions; data flow architecture; distributed memory multiprocessor; instruction level parallelism; large-grain data flow; load distribution strategy; multiple data; parallel execution; procedure activations; single instruction; three-level hierarchical hardware structure; token-passing; Algorithm design and analysis; Computational modeling; Computer architecture; Computer interfaces; Computer languages; Distribution strategy; Employment; Hardware; Mathematics; Parallel processing;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '92 . 'Computer Systems and Software Engineering',Proceedings.

Conference_Location

The Hague, Netherlands

Print_ISBN

0-8186-2760-3

Type

conf

DOI

10.1109/CMPEUR.1992.218492

Filename

218492