Verification strategy of the CATHEDRAL-I silicon compiler based on the SFG-tracing methodology

Author

Proesmans, F. ; Claesen, L. ; Genoe, M. ; Verlind, E.

Author_Institution

IMEC-DMV, Leuven, Belgium

fYear

1992

fDate

4-8 May 1992

Firstpage

17

Lastpage

22

Abstract

The application strategy is described of a new verification methodology on the CATHEDRAL-I silicon compiler. The basic goal is to prove the feasibility of an automated verification process based on the presented SFG-tracing concept. This methodology permits the overall evaluation of the lower-level implementation versus the high-level behavioral signal flow graph. Gradually, correspondences between specific signals, called references signals, at the different design levels are mapped during the architecture synthesis. Efficient behavior comparison can be started as soon as those relationships are traced accurately and completely. This task was handled with the aid of the compiled-code symbolic simulator COSMOS.<>

Keywords

VLSI; circuit layout CAD; formal verification; CATHEDRAL-I silicon compiler; SFG-tracing concept; application strategy; architecture synthesis; automated verification process; behavior comparison; compiled-code symbolic simulator COSMOS; design levels; high-level behavioral signal flow graph; lower-level implementation; references signals; verification methodology; Acceleration; Circuit simulation; Costs; Flow graphs; Integrated circuit synthesis; Product design; Signal design; Silicon compiler; Time to market; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '92 . 'Computer Systems and Software Engineering',Proceedings.

Conference_Location

The Hague, Netherlands

Print_ISBN

0-8186-2760-3

Type

conf

DOI

10.1109/CMPEUR.1992.218493

Filename

218493