Reliability assessment of microvias in HDI printed circuit boards

Accelerating adoption of CSP and flip-chip area array packaging for high performance and hand-held applications is the main driving force for high-density printed circuit boards and substrates. Ultrafine line HDI substrate technology is being developed as part of the System-on-a-Package (SOP) research and test bed efforts to meet these emerging requirements. To be adopted by industry, this novel technology must demonstrate the critical elements of high reliability and low cost processing. The high density interconnect (HDI) and microvias structures discussed in this paper, were fabricated on high Tg FR4 cores, measuring 300 mm × 300 mm in size, and contain up to 3 metal interconnect layers. They were fabricated using a sequential build-up process, and were subject to extensive liquid to liquid thermal shock testing. Shock testing revealed that reliability failures are process defect driven and do not correlate directly to microvia geometries. 75 μm microvias have successfully passed 2,000 cycles without failure, zero 50 μm vias failed before 1,000 cycles, and 25 μm microvias have passed 1,200 cycles with zero failures to date. Cross-sectioning of the failed components confirmed that failures were caused by process related defects, such as thin electrolytic copper plating. This paper discusses the reliability results of the PRC HDI microvias process, and how to improve the mechanical reliability of small photodefined microvias fabricated on similar laminates using similar processes