Will SOI have a life for the low-power market?

Author

Cai, Jin ; Ren, Zhibin ; Majumdar, Amlan ; Ning, Tak H. ; Yin, Haizhou ; Park, Dae-Gyu ; Haensch, Wilfried E.

Author_Institution

IBM Res. Div., IBM T. J. Watson Res. Center, Yorktown, NY

fYear

2008

fDate

6-9 Oct. 2008

Firstpage

15

Lastpage

16

Abstract

We discuss key challenges for SOI CMOS to achieve sub-100 pA/m leakage current required for low-standby power applications. Recent 45 nm data is used to illustrate the importance of junction engineering to mitigate SOI floating body effect for low leakage design. With device scaling towards 22 nm node, both bulk and SOI technologies are expected to hit a fundamental GIDL limit. Extremely-thin body SOI provides a scaling path for low-leakage SOI. Finally, we identify several unique SOI opportunities that can broaden its appeal to the low power market.

Keywords

CMOS integrated circuits; leakage currents; silicon-on-insulator; SOI CMOS; SOI floating body effect; junction engineering; leakage current; low-leakage SOI; low-power market; low-standby power applications; CMOS technology; Conference proceedings; Data engineering; Doping; Implants; Leakage current; MOSFETs; Parasitic capacitance; Power engineering and energy; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2008. SOI. IEEE International

Conference_Location

New Paltz, NY

ISSN

1078-621X

Print_ISBN

978-1-4244-1954-8

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2008.4656272

Filename

4656272