DocumentCode :
3167005
Title :
Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation
Author :
Furuhashi, Hironobu ; Shino, Tomoaki ; Ohsawa, Takashi ; Matsuoka, Fumiyoshi ; Higashi, Tomoki ; Minami, Yoshihiro ; Nakajima, Hiroomi ; Fujita, Katsuyuki ; Fukuda, Ryo ; Hamamoto, Takeshi ; Nitayama, Akihiro
Author_Institution :
Center for Semicond. Res.&Dev., Toshiba Corp., Yokohama
fYear :
2008
fDate :
6-9 Oct. 2008
Firstpage :
33
Lastpage :
34
Abstract :
A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.
Keywords :
DRAM chips; cellular arrays; doping profiles; fluctuations; numerical analysis; Gbit array functionality; cell array transistors; channel impurity concentration; fully-depleted floating body cell; numerical simulation; random dopant fluctuation; scalability; single transistor DRAM; Circuit simulation; Conference proceedings; Fluctuations; Microelectronics; Predictive models; Random access memory; Resource description framework; Scalability; Signal generators; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2008. SOI. IEEE International
Conference_Location :
New Paltz, NY
ISSN :
1078-621X
Print_ISBN :
978-1-4244-1954-8
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2008.4656281
Filename :
4656281
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3167005
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