Stable high-density FD/SOI SRAM with selective back-gate bias using dual buried oxide

Author

Kim, Keunwoo ; Kuang, Jente B. ; Gebara, Fadi ; Ngo, Hung C. ; Chuang, Ching Te ; Nowka, Kevin J.

Author_Institution

IBM T.J. Watson Res. Center, Yorktown Heights, NY

fYear

2008

fDate

6-9 Oct. 2008

Firstpage

37

Lastpage

38

Abstract

The proposed selective-back gate bias technique using dual BOX improves SRAM stability, reduce leakage power, and enhances sub-array access speed while preserving overall area efficiency. TCAD simulations show that nominal Read SNM is improved by 37%, and the cell is very immune to process variations such as RDF, TSi, and TBOX. Thus, it is very suitable for high-performance on-chip cache and SOC embedded applications beyond 45 nm FD/SOI technologies.

Keywords

SRAM chips; buried layers; cache storage; integrated circuit noise; silicon-on-insulator; technology CAD (electronics); FD-SOI SRAM; Si; TCAD simulations; dual buried oxide; high-performance on-chip cache; leakage power; random dopant fluctuations; selective back-gate bias technique; static noise margin; Capacitance; Degradation; FinFETs; Fluctuations; Inverters; Random access memory; Resource description framework; Stability; Substrates; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2008. SOI. IEEE International

Conference_Location

New Paltz, NY

ISSN

1078-621X

Print_ISBN

978-1-4244-1954-8

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2008.4656283

Filename

4656283