Electrical performance of compliant wafer level package

Author

Patel, Chirag S. ; Martin, Kevin ; Meindl, James D.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2001

fDate

2001

Firstpage

1380

Lastpage

1383

Abstract

As the demand for portable and high speed communication products grows, wafer level packages with high chip-to-chip bandwidth and low package parasitics are required. A Compliant Wafer Level Package (CWLP) technology has been developed to meet the growing demand of higher electrical performance at low cost. The electrical performance of the compliant wafer level package in terms of its package parasitics and chip-to-chip bandwidth is investigated in this paper

Keywords

packaging; chip-to-chip bandwidth; compliant wafer level package; electrical characteristics; high-speed communication product; package parasitics; portable communication product; Bandwidth; Electronics packaging; Etching; Fabrication; Lead; Polymers; Prototypes; Semiconductor device packaging; Voltage; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2001. Proceedings., 51st

Conference_Location

Orlando, FL

ISSN

0569-5503

Print_ISBN

0-7803-7038-4

Type

conf

DOI

10.1109/ECTC.2001.928013

Filename

928013

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3167187