Sub-45nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications

Author

Bol, D. ; Ambroise, R. ; Flandre, D. ; Legat, J.-D.

Author_Institution

Univ. Catholique de Louvain, Louvain-la-Neuve

fYear

2008

fDate

6-9 Oct. 2008

Firstpage

57

Lastpage

58

Abstract

The improved immunity of FD SOI technology against short-channel effects has been shown to offer a great interest for subthreshold logic in terms of delay and energy per operation at medium throughputs (108 Op/s). Moreover, the combination of an undoped channel with a metal gate extends this benefit to lower throughputs by a reduction of the minimum functional V_dd and static energy. This makes FD SOI with metal gate a strong candidate for sub-45 nm robust and energy-efficient subthreshold circuits.

Keywords

CMOS logic circuits; MOSFET circuits; delays; integrated circuit design; logic design; low-power electronics; silicon-on-insulator; MOSFET; Si; delay; fully-depleted SOI CMOS subthreshold logic circuit; metal gate; reduction; short-channel effects; size 45 nm; static energy; ultralow-power applications; undoped channel; CMOS logic circuits; CMOS technology; Capacitance; Circuit simulation; Fluctuations; Logic circuits; MOSFET circuits; Optical wavelength conversion; Predictive models; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2008. SOI. IEEE International

Conference_Location

New Paltz, NY

ISSN

1078-621X

Print_ISBN

978-1-4244-1954-8

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2008.4656292

Filename

4656292