Insights into gate-underlap design in double gate based 6-T SRAM cell for low voltage applications

The degradation of SRAM stability with gate length and supply voltage scaling is a serious concern [1-7]. In this work, we analyze the impact of gate-underlap design [8-9] on the performance of 6-T SRAM cell, based on independently addressable 22 nm Double Gate (DG) SOI MOSFETs for low voltage operation. The trade-offs associated with read/write requirements have been evaluated in terms of eight performance metrics (Table 1).