Title :
Multi-level pass-transistor logic for low-power ULSIs
Author :
Sasaki, Y. ; Yano, K. ; Yamashita, S. ; Chikata, H. ; Rikino, K. ; Uchiyama, K. ; Seki, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
Multi-level pass-transistor logic (MPL) removes the redundancy in conventional single-level pass-transistor circuits to improve both power and delay. MPL is synthesizable based on the multi-level binary decision diagram, a new logic representation, and it has the potential to replace CMOS in any synthesized control block of an MPU. Overall improvement in the product of power, delay, and area of 42% over CMOS is confirmed in actual microprocessor benchmark tests.
Keywords :
Boolean functions; MOS logic circuits; ULSI; multivalued logic circuits; binary decision diagram; low-power ULSI; multi-level BDD; multi-level pass-transistor logic; Binary decision diagrams; Boolean functions; CMOS logic circuits; Circuit synthesis; Data structures; Delay effects; Difference equations; Logic circuits; Multiplexing; Ultra large scale integration;
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
DOI :
10.1109/LPE.1995.482412
