High performance, energy efficient master-slave flip-flop circuits

This paper investigates performance, power and energy efficiency of several CMOS master-slave D-flip-flops (DFFs). To improve performance and energy efficiency, a push-pull DFF and a push-pull isolation DFF are proposed. Among the five DFFs compared, the proposed push-pull isolation circuit is found to be the fastest with the highest energy efficiency and a minimum data pulse width property. Effects of using DPL circuit and tri-state push-pull driver are studied. The impact of scaling supply voltage alone and scaling transistor threshold voltage with supply voltage on speed and power consumption of these circuits is also examined.