Title :
A virtual zero-time, monolithic systolic sorting array
Author :
Ericson, M.N. ; Britton, C.L., Jr. ; Bouldin, D.W.
Author_Institution :
Oak Ridge Nat. Lab., TN, USA
Abstract :
A virtual zero-time VLSI sorting chip is described. The chip SORTPIPE II has a systolic array architecture and implements the sinking sort algorithm. The basic functional module of the systolic array is detailed, and development techniques employed as well as functional simulation and results are presented
Keywords :
VLSI; systolic arrays; SORTPIPE II; sinking sort algorithm; systolic array architecture; very large scale integration; virtual zero-time VLSI sorting chip; Computational modeling; Computer architecture; Data processing; Hardware; Laboratories; Microcomputers; Software algorithms; Sorting; Systolic arrays; Very large scale integration;
Conference_Titel :
Southeastcon '90. Proceedings., IEEE
Conference_Location :
New Orleans, LA
DOI :
10.1109/SECON.1990.117876
