Title :
On cycle borrowing analyses for interconnected chips driven by clocks having different but commensurable speeds
Author_Institution :
Dept. of Comput. Eng., Lund Univ., Sweden
Abstract :
The author considers the construction of synchronous systems having components driven at different rates by different, but commensurable, clocks. Furthermore these systems are to be constructed using level-sensitive latches with the intent of exploiting cycle borrowing over the entire system. The author presents a framework in which the entire system is managed as a single clocked entity, and investigates a timing analysis technique for such systems. Results for small examples are presented. The interface between such chips is studied; no resynchronizers are required. Alternate clock waveforms, and their effect on analysis complexity, are discussed
Keywords :
circuit analysis computing; computational complexity; analysis complexity; clock waveforms; clocks; cycle borrowing analyses; interconnected chips; level-sensitive latches; synchronous systems; timing analysis; Boolean functions; Circuit synthesis; Clocks; Costs; Delay; Design methodology; Energy consumption; Independent component analysis; Internet; Timing;
Conference_Titel :
Application Specific Array Processors, 1992. Proceedings of the International Conference on
Conference_Location :
Berkeley, CA
Print_ISBN :
0-8186-2967-3
DOI :
10.1109/ASAP.1992.218580
