Clock distribution architectures for 3-D SOI integrated circuits

Author

Pavlidis, Vasilis F. ; Savidis, Ioannis ; Friedman, Eby G.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY

fYear

2008

fDate

6-9 Oct. 2008

Firstpage

111

Lastpage

112

Abstract

Three topologies to globally distribute a clock signal in 3-D circuits have been evaluated. A 3-D test circuit, based on the MITLL 3-D IC manufacturing process, has been designed, fabricated, and measured and is shown to operate at 1.4 GHz. Clock skew measurements indicate that a topology that combines the symmetry of an H-tree on the second plane and local meshes on the other two planes will result in low clock skew for 3-D circuits while consuming the lowest power as compared to the other investigated topologies.

Keywords

clocks; integrated circuit design; integrated logic circuits; logic design; monolithic integrated circuits; silicon-on-insulator; 3D SOI integrated circuits; 3D test circuit design; MITLL 3-D IC manufacturing process; clock distribution architectures; clock skew measurements; logic circuit; CMOS technology; Circuit testing; Circuit topology; Clocks; Etching; Fabrication; Integrated circuit interconnections; Integrated circuit technology; Network topology; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2008. SOI. IEEE International

Conference_Location

New Paltz, NY

ISSN

1078-621X

Print_ISBN

978-1-4244-1954-8

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2008.4656319

Filename

4656319