Realistic fault extraction for high-quality design and test of VLSI systems

Author

Gonçalves, F.M. ; Teixeira, J.P. ; Teiceira, J.P.

Author_Institution

INESC, Lisbon, Portugal

fYear

1997

fDate

20-22 Oct 1997

Firstpage

29

Lastpage

37

Abstract

The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled both in Manhattan and 45° geometries. Higher level design data, obtained in the top-down design flow, is used for realistic fault characterization. A sliding window algorithm is extended for fault extraction of non-orthogonal geometries. An accurate critical area evaluation algorithm is proposed to compute the probability of occurrence of the defects. Over 100,000 transistor ICs are analyzed for bridging defects

Keywords

VLSI; automatic test software; circuit analysis computing; fault diagnosis; integrated circuit design; integrated circuit testing; object-oriented methods; 45° geometries; DOTLab; Manhattan geometries; VLSI systems; bridging defects; critical area evaluation algorithm; fault characterization; high-quality design; high-quality test; higher level design data; lobs tool; nonorthogonal geometries; realistic fault extraction; sliding window algorithm; top-down design flow,; virtual test environment; BiCMOS integrated circuits; CMOS technology; Circuit faults; Circuit testing; Data mining; Electronic design automation and methodology; Information geometry; Signal design; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on

Conference_Location

Paris

ISSN

1550-5774

Print_ISBN

0-8186-8168-3

Type

conf

DOI

10.1109/DFTVS.1997.628306

Filename

628306