DocumentCode
3167967
Title
Optimizing FinFET geometry and parasitics for RF applications
Author
Kranti, Abhinav ; Raskin, Jean-Pierre ; Armstrong, G. Alastair
Author_Institution
Northern Ireland Semicond. Res. Centre (NISRC), Queen´´s Univ. Belfast, Belfast
fYear
2008
fDate
6-9 Oct. 2008
Firstpage
123
Lastpage
124
Abstract
A detailed analysis about the impact of parasitic capacitances/resistances and fin geometry in FinFETs for RF applications has been presented. RF FinFETs should be designed with Tfin/Lg of 0.6 and AR of 3, along with minimal fin spacing of 50 nm to achieve higher fT and fMAX values. Although FinFET will always exhibit higher parasitics than an equivalent planar technology, reduction of RSD to ITRS target specification, together with a minimal fin spacing Sfin, results in significant improvement in RF figures of merit.
Keywords
MOSFET; capacitance; millimetre wave field effect transistors; FinFET geometry optimization; RF application; parasitic capacitance; parasitic resistance; Application software; Computational geometry; Computer science; Conference proceedings; Controllability; FinFETs; Laboratories; Microwave devices; Parasitic capacitance; Radio frequency;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2008. SOI. IEEE International
Conference_Location
New Paltz, NY
ISSN
1078-621X
Print_ISBN
978-1-4244-1954-8
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2008.4656325
Filename
4656325
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