A 6-bit 150 MHz competition encoding flash analog-to-digital converter

Author

Chen, Cheng ; Guo, Yuhua ; Ren, Junyan ; Wang, Zhaogang ; Zhang, Qianling

Author_Institution

Syst. State Key Lab., Fudan Univ., Shanghai, China

Volume

2

fYear

2002

fDate

29 June-1 July 2002

Firstpage

926

Abstract

A CMOS 6 bit 150 MHz flash analog-to-digital converter, fully compatible with standard digital CMOS technology, is described. Compared with the conventional encoding structure, competition encoding can reduce the comparator´s power consumption as well as suppress the error code rate of the ADC output greatly. The chip, fabricated in standard 0.35 μm 3.3 V CMOS technology, occupies an area of 0.64×0.45 mm². Finally, some test results are presented.

Keywords

CMOS integrated circuits; analogue-digital conversion; coding errors; comparators (circuits); integrated circuit design; integrated circuit measurement; integrated circuit noise; 0.35 micron; 0.45 mm; 0.64 mm; 150 MHz; 3.3 V; 6 bit; ADC output error code rate; CMOS comparator power consumption; competition encoder structure; competition encoding flash analog-to-digital converters; noise tolerance; Analog-digital conversion; Application specific integrated circuits; CMOS technology; Digital systems; Encoding; Energy consumption; Signal to noise ratio; Testing; Voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on

Print_ISBN

0-7803-7547-5

Type

conf

DOI

10.1109/ICCCAS.2002.1178939

Filename

1178939