Design verification using logic tests

Design verification is the process of assuring that a design is error-free. Empirical design verification involves the running of test cases against the design. To be effective, `sufficient´ testing must be performed. But to be cost-effective as well, testing must be terminated when that point is reached. There is a lack of quantifiable metrics to guide the development of tests for digital logic design verification. The authors report on the results of experiments that indicate that fault simulation, which parallels the well-known mutation testing approach used in software design verification, can be used to grade the coverage of test cases used for hardware design verification