Low power considerations in the design of pipelined FIR filters

Author

Nagendra, C. ; Owens, R.M. ; Irwin, M.J.

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

fYear

1995

fDate

9-11 Oct. 1995

Firstpage

32

Lastpage

33

Abstract

This paper discusses some design considerations in building deeply pipelined FIR filters using CMOS technology. Filters are good candidates for studying various design trade-offs. They have a regular structure where the multiply-accumulate cells (MACs) have unit fan-out. Hence, the output capacitance and consequently, power and delay, are dominated by the interconnect and clocking scheme which scale with circuit size.

Keywords

CMOS digital integrated circuits; FIR filters; digital filters; digital signal processing chips; integrated circuit design; pipeline arithmetic; timing; CMOS technology; DSP chips; clocking scheme; delay; gate-pipelined MAC3 circuits; half-bit MAC2 designs; interconnect scheme; low power design; multiply-accumulate cells; output capacitance; pipelined FIR filters; regular structure; unit fan-out; Arthritis; Circuits; Clocks; Computer science; Design engineering; Digital signal processing; Encoding; Equations; Finite impulse response filter; Pipeline processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics, 1995., IEEE Symposium on

Conference_Location

San Jose, CA, USA

Print_ISBN

0-7803-3036-6

Type

conf

DOI

10.1109/LPE.1995.482452

Filename

482452