Accurate logic-level power estimation

In this work we propose a more accurate model for logic-level power estimation that overcomes the limitations of previous models, while keeping computational efficiency competitive with traditional gate-level power estimation based on transition activity. Our technique exploits a BDD-based symbolic model for describing the charge and discharge of parasitic (and load) capacitance and the flow of short circuit current. Lookup tables are used only for modeling the timing behavior of the circuit (as it is commonly done in full-delay simulation), therefore power simulation only marginally increases memory usage. Our method is highly accurate also for single gate (local) power estimate, allowing the individuation of critical gates during design optimization. We have implemented our techniques using VERILOG-XL as simulation platform, therefore maintaining full compatibility with design environments based on Verilog HDL.